An image sensor, such as a camera, captures images. The captured images are processed by a readout circuit in order to be displayed on a screen for viewing. For video applications in particular, it is desirable to use a high performance readout circuit that provides fast image processing. The larger the number of images to be processed, the faster the processing speed of the readout circuit needs to be.
Such a readout circuit comprises electronic components which impose limitations on the processing speed. This limits the general processing speed of the readout circuit.
U.S. Patent Application Publication No. 2007/0076109 discloses a readout circuit architecture which increases the processing speed for images captured by the readout circuit in spite of the limitations imposed by certain electronic components of the circuit. This architecture is based on duplicating a processing chain in the readout circuit in order to double the processing speed for captured images.
In this manner, the processing speed of such a readout circuit is increased in spite of the processing speed limitations of its electronic components.
With such an architecture, the captured image is independently processed in two parts. Then the two independently processed parts of the image are combined when reassembling the captured image for display, yielding a processed image corresponding to the entire captured image. This processed image can then be displayed. As a result, however, the displayed image may have edge artifacts between the two parts of the image that were processed independently.
Such edge artifacts can visibly degrade the quality of displayed images. When a readout circuit having an architecture such as the one described in U.S. Patent Application Publication No. 2007/0076109 is used, the processing provided is well-suited for images captured at high resolutions, but there is degradation of the displayed images when the two independently processed parts of the images are combined.